The present invention relates to charge pumps for producing voltages above a power supply voltage present in a circuit. In particular, the present invention provides a charge pump for creating a relatively large voltage (approximately 6-10 volts) above the Vdd voltage with respect to a supply rail Vss which is a preset voltage below Vdd, for example, 4 to 6 volts below Vdd. Such charge pump voltage supplies are needed to supply the high side power supplies for high side drivers of power switching circuits.
FIG. 1 shows a prior art charge pump that operates off a two phase clock. The clock signal comprises a signal clock CLK and the inverted-clock signal which is 180° out of phase with CLK.
This circuit operates as follows. When the clock CLK is high, C28 charges via M43 and M41 between Vdd and Vss as shown. The capacitor C28 charges to a voltage Vdd−Vss, as shown.
When the clock CLK goes low, M44 pulls the DP+ side of C28 to Vdd, current flows out of C28 polyside via floating polydiode D27 to VCP, the charge pump output. At that time, the voltage on C28 is above Vdd and turns on M42 gate thus allowing C29 to charge as shown between Vdd and Vss through M42 and M40, which is turned on by the inverted clock signal. When the inverted clock goes low, M45 is turned on, allowing C29 to discharge to VCP through diode D28. The charge pump voltage is provided through the diodes D27 and D28 to VCP. The cycle then repeats. The maximum VCP voltage is Vdd−Vss less the drop in either the diode D27 or D28, so approximately 5.4 volts given a 0.6 volt drop in the diode. A typical voltage at VCP will be approximately 5.2 volts.
Shoot through discharge of C28 via M41 is removed by the cross configuration connecting the gate of M41 to the opposite side, i.e., the C29 side which uses the inverted clock as an input. The same is true for the C29 side, with its cross connection of the gate of M42 to the C28 side. The DPplus epi capacitors Cepi1 and Cepi2 are parasitic capacitors that reduce efficiency.
The described charge pump only allows a voltage of slightly over 5 volts to be produced above the Vdd voltage if Vdd=6v. It is desirable to be able to produce a larger voltage, for example, approximately at least 6v above Vdd, and possibly as much as almost 10v, above Vdd. The described prior art circuit cannot provide such a voltage.